In recent years, the density of components are integrated into single integrated circuit devices has increased at a high rate. Examples of such high density circuits include dynamic random access memories (dRAMs), which are now being fabricated at 4 Mbit and 16 Mbit single-chip densities. In order to accomplish such complexities while maintaining the size of the chip at reasonable and manufacturable levels, the minimum feature size of the transistors and other components must of course be reduced. For dRAM devices, which have generally been the most densely integrated devices in the industry, the size of features such as MOS transistor gates is generally at the smallest size manufacturable by available technology. In the example of 16 Mbit dRAM devices, transistor gate widths are expected to be in the range of 0.5 to 0.7 microns.
It is well known that MOS transistors which have gate widths, and accordingly transistor channel lengths, which are of sub-micron dimensions are subject to time and voltage dependent phenomena to which larger transistors are not subject. An example of such a phenomenon is transistor performance degradation due to channel hot-carrier effects. While certain techniques are available to reduce the susceptibility of transistors to channel hot-carrier effects, such as providing graded junctions as described in U.S. Pat. No. 4,356,623 issued Nov. 2, 1982, and assigned to Texas Instruments Incorporated, the drain-to-source voltage nominally applied to the transistor structure remains a strong factor in the channel hot-carrier degradation of the transistor performance.
Furthermore, the storage element in dRAMs is commonly a thin film capacitor. It is well known that the data stored in dRAM capacitors may be upset by naturally occurring alpha particles. The degree to which data is lost in such events depends upon the capacitance of the memory cell, and accordingly the capacitance of modern dRAM cells is generally maintained above 35 fF for each cell, and preferably above 50 fF. Since it is desirable that the density of storage cells per unit area should be as large as possible, in order to maintain the necessary storage capacitance of 35 to 50 fF, the thickness of the capacitor dielectric must be reduced. Modern storage capacitors thus have dielectric thicknesses on the order of the equivalent of 10 nm of silicon dioxide, or less. However, with such thin capacitor dielectrics, both dielectric breakdown voltage and time-dependent dielectric breakdown rates degrade with thinner dielectrics, assuming a constant voltage applied thereacross.
For these reasons, the power supply voltages applied to such high density VLSI devices including dRAMs, other memories, and logic devices, are preferably reduced as the feature sizes decrease. In addition, since the power dissipation of the chip increases with increasing numbers of components integrated into the chip, a reduced power supply voltage would also reduce the device power dissipation. Many other circuits may still use a higher power supply voltages (e.g., 5 volts nominally) than is desired by the high density components described above (e.g., 3.3 volts), which makes the designer of systems incorporating these devices reluctant to provide an additional power supply in the system, due to the cost of such other supplies and the routing of an additional bias voltage.
It should also be noted that it is desirable that the performance of the integrated circuit should not vary strongly with the power supply voltage applied thereto, as such variation may increase the cost of production testing of the chip during its manufacture, but such variation may also cause system-level problems for the user.
Furthermore, in the field of dRAM devices, due to the large amount of thin capacitor dielectric on each device, manufacturers generally perform a "burn-in" operation during the test process of the chips. Burn-in is intended to stress the devices both by voltage and by temperature so that weak devices are removed from the population which is shipped to the user of the devices (i.e., removing the "infant mortality" portion of the reliability curve). On-chip regulation of the bias voltage for the memory array, for example, will preclude the direct application of the power supply voltage to the capacitors, however.
Referring first to FIG. 1, a power supply regulation system according to the prior art will be described in detail. The system of FIG. 1 provides a regulated voltage to memory array 125 when the circuit is biased at nominal V.sub.dd power supply voltages (e.g., from 4.5 volts to 6.0 volts) and provides a stress voltage to array 125 when a higher V.sub.dd level (e.g., above 6.0 volts) is applied, for example during such a burn-in operation. Reference voltage generator circuit 121, according to conventional designs such as a bandgap reference circuit and a voltage multiplier circuit, provides a regulated voltage on line MVA' to one input of comparator driver 122 and to stress, or burn-in, voltage generator circuit 115. The voltage on line MVA' is preferably at a voltage which is less than the nominal V.sub.dd power supply level during normal operation. For example, the voltage on line MVA' can be on the order of 3.3 volts.
Comparator driver 122 is of conventional design, and receives at its other input line VBIN' from burn-in voltage generator circuit 115. Comparator driver 122 in the system of FIG. 1 according to the prior art is constructed conventionally in such a fashion that array 125 is biased by the voltage which is the greater of the voltage on line MVA' and the voltage on line VBIN'.
Burn-in voltage generator circuit 115 according to the prior art system of FIG. 1 includes a differential amplifier 155 constructed according to a conventional design, including for example an n-channel MOS differential amplifier with a p-channel current mirror active load. Differential amplifier 155 is biased by an n-channel current source, which in turn is biased by a low voltage on line VREF, generated by reference voltage generator circuit 121. The second input to differential amplifier 155 is a voltage which is substantially three p-channel threshold voltages (i.e., 3V.sub.tp) below V.sub.dd, due to the series connection of p-channel transistors 150 between V.sub.dd and the second input to differential amplifier 155. Accordingly, the output of differential amplifier 155 on line VBIN' is at a high voltage when the value of V.sub.dd less 3V.sub.tp is greater than the voltage on line MVA' from reference voltage generator circuit 121.
The operation of the prior art system of FIG. 1 is illustrated by the dotted line portion of the transfer characteristic of FIG. 9. When the external power supply voltage V.sub.dd is above a certain level for operation, but below a value of approximately 6.3 volts, in this example, the bias of array 125 is at the voltage of line MVA', which in this case is on the order of 3.3 volts, as generated by reference voltage generator circuit 121. However, when V.sub.dd exceeds the voltage on line MVA' by 3V.sub.tp (V.sub.tp in this example being on the order of 1.0 volts), differential amplifier 155 will drive line VBIN' to the higher voltage of V.sub.dd less 3V.sub.tp. Comparator driver 122 will, in turn, present this higher voltage to array 125. As the external power supply voltage V.sub.dd continues to rise, the voltage applied to array 125 also rises, following the transfer characteristic shown by the dotted line in FIG. 9. In this way, the system of FIG. 1 according to the prior art can apply a stress voltage to array 125 which varies with V.sub.dd, so that a burn-in or other stress operation can be performed.
The system of FIG. 1 has limitations in its flexibility of operation, however. If, for example, a certain high stress voltage were desired to be applied to array 125, for example, a stress voltage on the order of 7.0 volts, according to the above-described example, an external V.sub.dd voltage of 10.0 volts is necessary. However, modern sub-micron transistors may not be capable of withstanding the stress of a 10.0 volt bias, and while the array in the system of FIG. 1 would not receive such a high voltage due to the operation of the system, there would be transistors in the periphery of the device (e.g., those transistors in reference voltage generator 121 and in burn-in voltage generator circuit 115) which are biased directly by V.sub.dd. Limitations on the voltage applied to these transistors could thus limit the maximum stress voltage which the system of FIG. 1 could apply to array 125.
In order to apply such a high stress voltage to array 125 according to the system of FIG. 1 without damaging peripheral transistors, the designer of the system could reduce the number of transistors 150 in burn-in voltage generator circuit 115, so that the difference between V.sub.dd and the voltage of line VBIN' during stress conditions would be reduced. By reducing the number of transistors 150 in burn-in voltage generator circuit to two, for example, a 7.0 volt stress bias could be applied to array 125 with only 9.0 volts applied to V.sub.dd. However, if the number of transistors 150 in the system of FIG. 1 were reduced to two, the system would apply the stress voltage at a lower level of V.sub.dd, in this case when V.sub.dd was 2V.sub.tp over the voltage on line MVA'. With a V.sub.tp on the order of 1.0 volts and the voltage on line MVA' at 3.3 volts in this example, the stress condition would be applied to array 125 when V.sub.dd exceeded 5.3 volts. Since a V.sub.dd of 5.3 volts is within the specified normal operating range of V.sub.dd for conventional dRAM devices, though, such a construction of burn-in voltage generator circuit 115 would result in stress of array 125 during normal operation.
It should therefore be evident that the system of FIG. 1 provides quite limited flexibility to the designer of the circuit using such a power regulation system, especially in selecting a stress voltage.
In addition, VLSI devices including small feature sizes as described above also may be damaged by overvoltage conditions which are inadvertently applied to the device by the user, or during test operations. Furthermore, since complementary MOS (i.e., CMOS) technology is now commonly used in VLSI circuits due to its reduced power dissipation and fast performance, latchup of CMOS structures at excessive power supply voltages, due to the parasitic thyristors inherent in CMOS, is also a concern.
It is therefore an object of this invention to provide an on-chip system for regulating the power supply voltage applied to various portions of a large scale integrated circuit.
It is therefore another object of this invention to provide such an on-chip system for regulating its internal bias voltages so that the performance of the chip is relatively stable with respect to the power supply voltage.
It is therefore another object of this invention to provide such a system which can apply a stress voltage to portions of the device, responsive to the power supply voltage applied externally to the device.
It is therefore another object of this invention to provide such a system which allows the stress voltage to be determined independently from the regulated internal bias voltage.
It is therefore another object of this invention to provide such a system which clamps internal bias voltages responsive to an excessive externally applied power supply voltage.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification, together with the drawings.